The present invention relates generally to fabrication of semiconductor devices, and more specifically to packaging integrated circuits.
Packaged integrated circuit (IC) having plastic, epoxy or resin packages encapsulating the die (semiconductor chip) and a portion of the lead frame and leads are produced using a variety of methods.
U.S. Pat. No. 5,891,377 to Libres et al. describes lead frames, mold chases and mold flashes in a dambarless leadframe process.
U.S. Pat. No. 4,615,857 to Baird describes an encapsulating method for reducing flash.
U.S. Pat. No. 6,309,916 B1 to Crowley et al. describes a method of molding a plastic body of a semiconductor package.
U.S. Pat. No. 5,949,132 to Libres et al. describes a method and apparatus for encapsulating an integrated circuit die and leadframe assembly using dambarless leadframes.
Accordingly, it is an object of the present invention to provide a improved method of assembling an integrated circuit package with an exposed die back.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a die attached to a substrate by connectors is provided. The die having a backside. Encapsulate is formed around the die and over the backside of the die to form an encapsulated package. The encapsulate overlying the backside of the die and a portion of the backside of the die are removed using a backside exposure process to complete the assembled package having the die exposed.